Photo sensors comprising two-dimensional pixel fields can classified by their readout techniques. Active pixels are fabricated with complementary metal oxide semiconductors (CMOS) technology.
In a CMOS photo sensor, the charge-to-voltage conversion occurs inside each pixel. The photo signal is converted from electrons to a voltage. The signal is typically buffered by a source-follower transistor and is then transferred via select-switches to an output bus. The parallel column busses are connected via column buffer circuits to a multiplexer. There the signal is amplified and connected to the output.
The limitation of CMOS photo sensor is the conversion of the charge to a voltage. The pixel works in the voltage domain and is afflicted by noise of the readout circuit. The limited space in the pixel does not allow for low-noise circuitry.
A further limitation is the space needed by the output circuit in the pixel. Especially 3D imaging pixels with an arbitrary number of n output paths, a large proportion of chip real estate is claimed for the output circuit. Each storage area needs a separate output path with source follower and select-transistor. This consumes space and reduces the fill factor.
The advantage of CMOS devices is that one or more active transistors can be integrated into each of the pixels and thus the pixels become fully addressable. In contrast, charge coupled device (CCD) sensors use architectures in which charge carriers are transferred through storage cells to a sensor readout stage, just one dedicated for one sensor. The transport of the signal happens in the charge domain and therefore a high image quality with low noise is obtained.
In more detail, compared to CMOS sensors, the typical CCD sensor architecture has no active transistors in the pixel itself. The charge is moved laterally through the semiconductor, enforced by the voltage distribution applied to the CCD gate structure. Thus, the whole signal transport happens in the charge domain so that the signal is less distorted by noise than in a CMOS readout circuit or system.
A typical CCD architecture has three basic functions: 1) charge collection in the photo-sensitive area, 2) charge transfer through a CCD chain, and 3) the conversion of the charge in a measurable voltage (sense node and amplification).
The electrons are collected in the sensitive area of the pixel. After the integration period the signal is shifted to the readout register in the charge transfer step. This is used to transport the signal to the sense node typically at the border of the pixel field via a transport chain. The shift cycle happens depending on the architecture in 2 to 4 phases.
The sensitive area can be part of the transport chain itself but in most cases the pixel structure and the readout structure is separated. The CCD readout procedure can be distinguished by the number of phases needed for one shift to the next storage cell. There are 4 phase-, 3 phase and 2-phase CCD devices.
All known CCD transport chains suffer from the fact that one storage cell requires several gates that are large enough in order to store the full signal. This, however, limits the storage capacitance per storage cell significantly.
The CCD transport procedures are distinguished by the numbers of phase cycles they need for one charge shift from one pixel or storage element to the next.
In any case, the charge movement is realized by manipulating appropriately the gate voltages in such a way that the charge carriers can laterally follow the potential distribution into the direction of lowest energy without seeing any potential barrier. If the charge carriers to be collected are electrons, the point of lowest energy is at highest potential; and for holes it is the opposite.
Several smart pixel sensor developments made use of combined CCD/CMOS process technologies in the past. An overview of different smart sensor concepts in CCD/CMOS process technology is given by Seitz, et al (“Smart optical and image sensors fabricated with industrial CMOS/CCD semiconductor processes”, in SPIE Vol. 1900, pp. 21-30, 1993). One major application field where combined CCD/CMOS processes are used is found in 3D time of flight (TOF) imaging. The specific requirements of those pixels are CCD transistors for high speed demodulation and the utilization of active CMOS transistors for the readout structure. This demands a CMOS process with an additional CCD option, which mainly consists of the feature of overlapping gates and a buried channel implantation. This combined or hybrid process can be used to implement advanced CCD readout structures.